Recently, in an information processing device such as a server or a computer, the capability (bandwidth, in particular) of a component such as a central processing unit (CPU) has been largely improved. To improve the total bandwidth of the entire information processing device, speeding-up is requested for a communication circuit configured to communicate data between chips such as CPUs, between a plurality of elements in each chip, or between a plurality of circuit blocks in some cases. Speeding-up is also requested for a communication circuit configured to communicate data between boards or bodies in some cases. In such a communication circuit for which fast data communication through electrical communication or optical communication is requested, for example, a signal equalizer (equalizer) is used to compensate data signal degradation occurring on a communication path.
One of such equalizers is a decision feedback equalizer (DFE). The DFE is an equalizer configured to reduce the influence of inter symbol interference (ISI) superimposed on a data signal. At each decision of an input data signal by a comparator, the DFE directly subtracts the ISI from the data signal by changing a decision threshold of the comparator by an amount determined in accordance with a weighted sum of a “past decision result” and a “coefficient (DFE coefficient) set from the outside”. Thus, the opening amount of an eye increases as the DFE coefficient is closer to the value of the ISI, and the influence of the ISI is reduced accordingly.
In a DFE of a disclosed conventional technology, a weighting adder is incorporated inside a comparator. In the conventional technology, the DFE coefficient is set by changing the number of transistors turned on in accordance with an external digital control signal, the transistors connecting latches included in the comparator and a power source.
Examples of the related art include Japanese Laid-open Patent Publication No. 2005-341582, International Publication Pamphlet No. WO 2009/113462, Sam Palermo, ECEN689: Special Topics in High-Speed Links Circuits and Systems, Spring 2010, Class Notes Lecture 19, Texas A &amp; M University, and T. Shibasaki, et al., “A 56-Gb/s Receiver Front-End with a CTLE and 1-Tap DFE in 20-nm CMOS”, IEEE Symp. VLSI Circuits, pp. 112-113, June 2014.